Implementation of a DSSS MODEM ASIC chip for wireless LAN

IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation

Volumn , Issue , 1998, Pages 243-252

  Chang, Hyun Man ^a   Sunwoo, Myung H ^a  

^a Ajou University   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; BIT ERROR RATE; COMMUNICATION CHANNELS (INFORMATION THEORY); COMPUTER SIMULATION; DIRECT SEQUENCE SYSTEMS; LOCAL AREA NETWORKS; MATHEMATICAL MODELS; MICROPROCESSOR CHIPS; MODEMS; PHASE SHIFT KEYING; SPURIOUS SIGNAL NOISE; WIRELESS TELECOMMUNICATION SYSTEMS;

VERILOG HARDWARE DESCRIPTION LANGUAGES (VHDL);

APPLICATION SPECIFIC INTEGRATED CIRCUITS;

EID: 0031642241     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (12)