Test structures to characterize a novel circuit fabrication technique that uses offset lithography

IEEE International Conference on Microelectronic Test Structures

Volumn , Issue , 1998, Pages 39-44

  Walton, A J ^a   Stevenson, J T M ^a   Fallon, M ^a   Evans, P S A ^a   Ramsey, B J ^a   Harrison, D ^a  

^a UNIVERSITY OF EDINBURGH   (United Kingdom)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC RESISTANCE; INTEGRATED CIRCUIT TESTING; LITHOGRAPHY; MICROELECTRONICS; PRINTED CIRCUIT MANUFACTURE; SEMICONDUCTOR DEVICE STRUCTURES; SUBSTRATES; THIN FILM DEVICES;

METAL-LOADED INK; OFFSET LITHOGRAPHY; SHEET RESISTANCE;

PRINTED CIRCUIT BOARDS;

EID: 0031639075     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)