Electrical modeling of the chip scale BGA

Proceedings - Electronic Components and Technology Conference

Volumn Part F133492, Issue , 1998, Pages 1280-1285

  Caggiano, M F ^a   Brush, R M ^a   Kleban, J T ^a   Chuaypradit, P J ^a  

^a RUTGERS UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DATA HANDLING; MILITARY APPLICATIONS; NETWORK COMPONENTS; COMPUTER SIMULATION; COMPUTER SOFTWARE; SEMICONDUCTOR DEVICE MODELS;

COMMERCIAL ELECTRONICS; ELECTRICAL MODELING; PACKAGE MODELING; PARASITIC EFFECT; PARTIAL INFORMATION; PROGRAM OPERATION; ROUGH APPROXIMATIONS; WHOLE PROCESS; CHIP SCALE BALL GRID ARRAYS (CSBGA);

BALL GRID ARRAYS; ELECTRONICS PACKAGING;

EID: 0031636957     PISSN: 05695503     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ECTC.1998.678906     Document Type: Conference Paper

References (5)

1. M. F. Caggiano, "A PC Program That Generates a Model of the Parasitics for BGA Packages, " Proceedings IEEE 45th Electronic Components and Technology Conference, Vol. 1, May 1995.
2. M. F. Caggiano, "RF Electrical Measurements Comparisons of a 64 TQFP with a Computer Generated Model, " Applied Microwave and Wireless, Vol. 9 No. 4, July/August 1997.
3. F. W. Grover, "Inductance Calculations, Working Formulas and Tables", Dover Publications, Inc, New York, NY 1973.
4. Walker, "Capacitance, Inductance, Crosstalk Analysis", Artech House, Inc. Boston, Massachusetts, 1990.
5. A. J. Rainal, "Computing Inductive Noise of Chip Packages, " AT&T Bell Laboratories Technical Journal, Vol. 63, January 1984.