A Re-engineering approach to low power FPGA design using spfd

Proceedings - Design Automation Conference

Volumn , Issue , 1998, Pages 722-725

  Hwang, Jan Min ^a   Chiang, Feng Yi ^a   Hwang, TingTing ^a  

^a NATIONAL TSING HUA UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

FIELD PROGRAMMABLE GATE ARRAYS (FPGA); STRESS ANALYSIS; TABLE LOOKUP; FUNCTIONS; LOGIC DESIGN; REENGINEERING;

FIELD PROGRAMMABLES; LOOK UP TABLE; LOW TRANSITION; LOW-POWER FPGAS; PLACEMENT AND ROUTING; PROGRAMMABLE LOGIC;

INTEGRATED CIRCUIT DESIGN; FIELD PROGRAMMABLE GATE ARRAYS;

SET OF PAIRS OF FUNCTIONS TO BE DISTINGUISHED (SPFD);

EID: 0031635671     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)

1. S.D.Brown, R.J.Francis, J.Rose and Z.G.Vranesic. Field-Programmable Gate Arrays. Kluwer Academic Publishers, 1992.
2. V.Tiwari, P.Ashar and S.Malik. Technology Mapping for Low Power. Proc. of Design Automation Conference, 1993, pp.74-79.
3. M.Alidina, J.Monteiro, S.Devadas, A.Ghosh and M.Papaefthymiou. Precomputation-Based Sequential Logic Optimization for Low Power. IEEE Transactions on VLSI Systems, Vol.2, NO.4, December 1994.
4. Chao-Shen Chen, Ting-Ting Hwang. Low Power FPGA Design-A Re-engineering Approach. Proc. of Design Automation Conference, 1997.
5. Shigeru Yamashita, Hiroshi Sawada and Akira Nagoya. A New Method to Express Functional Permissibilities for LUT based FPGAs and Its Applications. Proc. of International Conference on Computer Aided Design, 1996.