Low resistance dual damascene process by new Al reflow using Nb liner

Digest of Technical Papers - Symposium on VLSI Technology

Volumn , Issue , 1998, Pages 48-49

  Wada, J ^a   Oikawa, Y ^a   Katata, T ^a   Nakamura, N ^a   Anand, M B ^a  

^a TOSHIBA CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ALUMINUM; ELECTRIC RESISTANCE; NIOBIUM; SILICON WAFERS;

LOW RESISTANCE DUAL DAMASCENE PROCESS;

ULSI CIRCUITS;

EID: 0031634348     PISSN: 07431562     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)