Design concept for the low turn-off loss 4.5 kV trench IGBT

IEEE International Symposium on Power Semiconductor Devices & ICs (ISPSD)

Volumn , Issue , 1998, Pages 51-54

  Takahashi, T ^a   Uenishi, A ^a   Kusunoki, S ^a   Minato, T ^a   Nakamura, H ^a   Aono, S ^a   Nakamura, K ^a   Nitta, T ^a   Harada, M ^a  

^a MITSUBISHI ELECTRIC CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE; CARRIER CONCENTRATION; COMPUTER SIMULATION; ELECTRIC CURRENTS; ELECTRIC LOSSES; ELECTRIC NETWORK ANALYSIS; ELECTRIC POTENTIAL; GATES (TRANSISTOR); INTEGRATED CIRCUIT LAYOUT; IONIZATION OF SOLIDS; MOSFET DEVICES; SEMICONDUCTOR DEVICE STRUCTURES;

HIGH VOLTAGE TRENCH INSULATED GATE BIPOLAR TRANSISTORS (IGBT); MILLER-CAPACITANCE;

BIPOLAR TRANSISTORS;

EID: 0031633219     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)