Heuristic algorithm to solve constrained via minimization for three-layer routing problems

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 6, Issue , 1998, Pages 254-257

  Takahashi, Kazuhiro ^a   Watanabe, Toshimasa ^a  

^a HIROSHIMA UNIVERSITY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTATIONAL COMPLEXITY; GRAPH THEORY; HEURISTIC METHODS; INTEGRATED CIRCUIT LAYOUT; MATHEMATICAL MODELS; MINIMIZATION OF SWITCHING NETS;

VIA MINIMIZATION BY BREADTH FIRST SEARCH (VMBF);

VLSI CIRCUITS;

EID: 0031632297     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (11)