Two-loop third-order multistage ΔΣ frequency to digital converter

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 1, Issue , 1998, Pages 408-411

  Riley, Thomas A D ^a   Filiol, Norman M ^a   Copeland, Miles A ^a  

^a CARLETON UNIVERSITY   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

CODING ERRORS; DIGITAL SIGNAL PROCESSING; PHASE LOCKED LOOPS; SPURIOUS SIGNAL NOISE;

FREQUENCY TO DIGITAL CONVERSION;

DELTA SIGMA MODULATION;

EID: 0031632253     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (7)