Impact of data characteristics and hardware topology on hardware selection for low power DSP

Proceedings of the International Symposium on Low Power Design

Volumn , Issue , 1998, Pages 94-96

  Keane, Gareth ^a   Spanier, Jonathan ^a   Woods, Roger ^a  

^a QUEEN'S UNIVERSITY BELFAST   (United Kingdom)

Author keywords

[No Author keywords available]

Indexed keywords

ADDERS; COMPUTER SIMULATION; DESIGN; DIGITAL SIGNAL PROCESSING; ELECTRIC NETWORK SYNTHESIS; ELECTRIC NETWORK TOPOLOGY; ESTIMATION; MULTIPLYING CIRCUITS; OPTIMIZATION;

CARRY-SAVE ARRAY; MULTIPLIER STRUCTURES; OPTIMUM HARDWARE SELECTION; WALLACE TREE MULTIPLIERS;

ELECTRIC POWER SUPPLIES TO APPARATUS;

EID: 0031632130     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (7)