Shallow trench isolation with SiN guard-ring for sub-quarter micron CMOS technologies

Digest of Technical Papers - Symposium on VLSI Technology

Volumn , Issue , 1998, Pages 210-211

  Ogura, Takashi ^a   Yamamoto, Toyoji ^a   Saito, Yukishige ^a   Hayashi, Yoshihiro ^a   Mogami, Tohru ^a  

^a NEC CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; LSI CIRCUITS; SILICA; SILICON NITRIDE;

REVERSE NARROW CHANNEL EFFECTS; SHALLOW TRENCH ISOLATION (STI);

INTEGRATED CIRCUIT MANUFACTURE;

EID: 0031630375     PISSN: 07431562     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (3)