Pipelined architecture of fast modular multiplication for RSA cryptography

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 2, Issue , 1998, Pages 121-124

  Sheu, Jia Lin ^a   Shieh, Ming Der ^a   Wu, Chien Hsing ^a   Sheu, Ming Hwa ^a  

^a NATIONAL YUNLIN UNIVERSITY OF SCIENCE AND TECHNOLOGY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTATIONAL METHODS; COMPUTER ARCHITECTURE; CRYPTOGRAPHY; PIPELINE PROCESSING SYSTEMS; VLSI CIRCUITS;

CARRY-SAVE ADDITION; FAST MODULAR MULTIPLICATION;

MULTIPLYING CIRCUITS;

EID: 0031630274     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (12)