Design of a collision detection VLSI processor based on minimization of area-time products

Proceedings - IEEE International Conference on Robotics and Automation

Volumn 4, Issue , 1998, Pages 3691-3696

  Hariyama, M ^a   Kameyama, M ^a  

^a TOHOKU UNIVERSITY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CAMS; GENERAL PURPOSE COMPUTERS; PARALLEL PROCESSING SYSTEMS; VLSI CIRCUITS; ALGORITHMS; COLLISION AVOIDANCE; COMPUTER ARCHITECTURE; CONSTRAINT THEORY; ITERATIVE METHODS; MATHEMATICAL TRANSFORMATIONS; MOTION PLANNING; OPTIMIZATION; PIPELINE PROCESSING SYSTEMS; ROBOTICS;

AREA MINIMIZATION; CO-ORDINATE TRANSFORMATION; COLLISION DETECTION; GENERAL PURPOSE PROCESSORS; PARALLEL COORDINATES; PIPELINED ARCHITECTURE; SYSTEMATIC METHODOLOGY; TIME CONSTRAINTS;

INTEGRATED CIRCUIT DESIGN; INTELLIGENT ROBOTS;

AREA TIME PRODUCTS; BIT SERIAL PIPELINED ARCHITECTURES;

EID: 0031629356     PISSN: 10504729     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ROBOT.1998.681407     Document Type: Conference Paper

References (4)

1. M. Hariyama and M. Kameyama, "Collision Detection VLSI Processor for Intelligent Vehicles Based on Efficient Coordinate Transformation Scheme, " in Proc. of International Conference on Industrial Electronics, Control, and Instrumentation, Vol. 2, pp.755-760, 1996.
2. T. Yamagata, M. Mihara, T. Hamamoto, Y. Mural, T. Kobayashi, M. Yamada, and H. Ozaki, "A 288-kb Fully Parallel Content Addressable Memory Using a Stacked-Capacitor Cell Structure, " IEEE J. Solid-State Circuits, Vol. 27, No. 12, pp.1927-1933, 1992.
3. I. Okabayashi, H. Kotani and H. Kadota, "A Proposed Structure of 4 Mbit Content-Addressable and Sorting Memory, " 1990 symp. on VLSI Circuits, pp.109-110, 1990.
4. M. Hariyama and M. Kameyama, "Design of a CAM-Based Collision Detection VLSI Processor for Robotics, " IEICE Trans., Vol.E77-C, No.7, pp.1108-1115, 1994.