Divide-by-4 circuit implemented in low voltage, high speed silicon bipolar topology

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 2, Issue , 1998, Pages 133-136

  Schuppener, Gerd ^a   Mokhtari, Mehran ^a   Tenhunen, Hannu ^a  

^a ROYAL INSTITUTE OF TECHNOLOGY   (Sweden)

Author keywords

[No Author keywords available]

Indexed keywords

BIPOLAR INTEGRATED CIRCUITS; CMOS INTEGRATED CIRCUITS; ELECTRIC FREQUENCY MEASUREMENT; ELECTRIC NETWORK ANALYSIS; ELECTRIC NETWORK TOPOLOGY; EMITTER COUPLED LOGIC CIRCUITS; ENERGY UTILIZATION; FLIP FLOP CIRCUITS; INTEGRATED CIRCUIT LAYOUT; SEMICONDUCTING SILICON;

DIVIDE-BY-FOUR CIRCUITS;

DIVIDING CIRCUITS (ARITHMETIC);

EID: 0031628207     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (4)