Design and implementation of high performance dynamic 64-bit parallel adder with enhanced testability

Proceedings of the Custom Integrated Circuits Conference

Volumn , Issue , 1998, Pages 519-522

  Hwang, W ^a   Gristede, G D ^a   Sanda, P N ^a   Wang, S Y ^a   Heidel, D F ^a  

^a IBM RESEARCH   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; ELECTRIC NETWORK SYNTHESIS; ENERGY DISSIPATION; INTEGRATED CIRCUIT LAYOUT; INTEGRATED CIRCUIT TESTING; LOGIC GATES; MICROPROCESSOR CHIPS; PARALLEL PROCESSING SYSTEMS; PULSE ANALYZING CIRCUITS;

DYNAMIC PARALLEL ADDERS;

ADDERS;

EID: 0031627588     PISSN: 08865930     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)