A high level synthesis system for VLSI image processing applications

VLSI Design

Volumn 7, Issue 4, 1998, Pages 321-336

  Verdier, François S ^a   Zavidovique, Bertrand ^b  

^a ETCA Syst de Perception Laboratory   (France)

^b UNIVERSITÉ PARIS SACLAY   (France)

Author keywords

Control optimization; Embedded systems; Functional decomposition; High level synthesis; Image processing automata; VLSI architectures

Indexed keywords

ALGORITHMS; CONTROL SYSTEM SYNTHESIS; DATA FLOW ANALYSIS; ELECTRIC NETWORK SYNTHESIS; EMBEDDED SYSTEMS; GRAPH THEORY; IMAGE PROCESSING; PREDICTIVE CONTROL SYSTEMS; RANDOM PROCESSES; SIMULATED ANNEALING;

DATA FLOW EMULATORS; DATA-PATH COMPLETION; DATA-PATH SYNTHESIS; HIGH LEVEL SYNTHESIS (HLS) SYSTEMS;

VLSI CIRCUITS;

EID: 0031626317     PISSN: 1065514X     EISSN: None     Source Type: Journal    
DOI: 10.1155/1998/95421     Document Type: Article

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