Hierarchical process simulation for nano-electronics

VLSI Design

Volumn 6, Issue 1-4, 1998, Pages 385-391

  Dutton, Robert W ^a,c,d,e,f,g   Kan, Edwin C ^a,b,e,h,i,j  

^a Stanford University   (United States)

^b Cornell University   (United States)

^c UNIVERSITY OF CALIFORNIA   (United States)

^d Department of Electrical Engineering ^*  (United States)

^e STANFORD UNIVERSITY   (United States)

^f IEEE   (United States)

^g NATIONAL ACADEMY OF ENGINEERING   (United States)

^h NATIONAL TAIWAN UNIVERSITY   (Taiwan)

ⁱ UNIVERSITY OF ILLINOIS AT URBANA CHAMPAIGN   (United States)

^j Dawn Technologies

more..

Author keywords

Hierarchy; Interconnects; Parallel computing; Technology CAD

Indexed keywords

COMPUTER AIDED DESIGN; COMPUTER SIMULATION; COMPUTER SOFTWARE; HIERARCHICAL SYSTEMS; MICROELECTRONIC PROCESSING; NANOSTRUCTURED MATERIALS;

NANOELECTRONICS;

SEMICONDUCTOR DEVICES;

EID: 0031625443     PISSN: 1065514X     EISSN: None     Source Type: Journal    
DOI: 10.1155/1998/19402     Document Type: Article

References (13)

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