Exploiting sleep mode for memory partitioning and other applications

VLSI Design

Volumn 7, Issue 3, 1998, Pages 271-287

  Farrahi, Amir H ^{a,b,c,d,e,f,g,h,i}   Téllez, Gustavo E ^a,j   Sarrafzadeh, Majid ^a  

^a Northwestern University   (United States)

^b IBM T J WATSON RESEARCH CENTER   (United States)

^c SHARIF UNIVERSITY OF TECHNOLOGY   (Iran)

^d ILLINOIS INSTITUTE OF TECHNOLOGY   (United States)

^e NORTHWESTERN UNIVERSITY   (United States)

^f Software and Hardware Support Team   (Iran)

^g Vista Technologies Inc   (United States)

^h CADENCE DESIGN SYSTEMS   (United States)

ⁱ IEEE

^j RENSSELAER POLYTECHNIC INSTITUTE   (United States)

more..

Author keywords

NP Completeness; Partitioning; Power minimization; Sleep mode

Indexed keywords

COMPUTATIONAL COMPLEXITY; DATA STORAGE EQUIPMENT; ELECTRIC NETWORK ANALYSIS; ELECTRIC NETWORK SYNTHESIS; ENERGY UTILIZATION; PROBLEM SOLVING;

MEMORY PARTITIONING; SLEEP MODE OPERATION;

VLSI CIRCUITS;

EID: 0031625070     PISSN: 1065514X     EISSN: None     Source Type: Journal    
DOI: 10.1155/1998/50491     Document Type: Article

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