Design and implementation of the NUMAchine multiprocessor

Proceedings - Design Automation Conference

Volumn , Issue , 1998, Pages 66-69

  Grbic, A ^a   Brown, S ^a   Caranci, S ^a   Grindley, R ^a   Gusat, M ^a   Lemieux, G ^a   Loveless, K ^a   Manjikian, N ^b   Srbljic, S ^c   Stumm, M ^a   Vranesic, Z ^a   Zilic, Z ^d  

^a UNIVERSITY OF TORONTO   (Canada)

^b QUEEN S UNIVERSITY   (Canada)

^c UNIVERSITY OF ZAGREB   (Croatia)

^d NOKIA RESEARCH CENTER   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COST EFFECTIVENESS; LOGIC DEVICES; MULTIPROCESSING SYSTEMS; COMPUTER ARCHITECTURE; PROGRAMMABLE LOGIC CONTROLLERS;

CC-NUMA; COST EFFECTIVE; DESIGN AND IMPLEMENTATIONS; HARDWARE FEATURES; OFF-THE-SHELF COMPONENTS; PARALLEL SOFTWARE DEVELOPMENT; PROGRAMMABLE LOGIC DEVICE; RESEARCH VEHICLES;

SOFTWARE DESIGN; MULTIPROCESSING SYSTEMS;

NUMACHINE ARCHITECTURE;

EID: 0031623468     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (8)

1. A. Agarwal et al. The MIT Alewife Machine: Architecture and Performance. In Proc. of the 22nd Annual ISCA, pages 2-13, June 1995.
2. S. Brown et al. Experience in Designing a Large-Scale Multiprocessor usign Field-Programmable Devces and Advanced CAD Tools. In Proc. of the 33rd DAC, pages 427-432, Las Vegas, NV, June 1996.
3. K. Farkas, Z. Vranesic, and M. Stumm. Scalable cache consistency for hierarchically-structured multiprocessors. J. of Super- computing, pages 345-368, 1995.
4. J. Kuskin et al. The Stanford FLASH Multiprocessor. In Proc. of the 21st Annual ISCA, pages 302-313, Chicago, IL, May 1994.
5. D. Lenoski et al. The DASH prototype: Implementation and performance. In Proc. of the 19th Annual ISCA, pages 92-103, Gold Coast, Australia, May 1992.
6. G. Ravindran and M. Stumm. A Performance Comparison of Hierarchical Ring- And Mesh-Connected Multiprocessor Networks. In Proc. of the Third International Symposium on HPCA, pages 58-69, San Antonio, Texas, February 1997.
7. Z. Vranesic et al. The NUM Achine Multiprocessor. Technical Report CSRI-324, Computer Systems Research Institute, University of Toronto, 1995.
8. Z. Zilic et al. Designing for High Speed-Performance in CPLDs and FPGAs. In The 3rd Canadian Workshop on Field- Programmable Devices (FPD'95), pages 108-113, May 1995.