Dynamic-floating-gate design for output ESD protection in a 0.35-μm CMOS cell library

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 2, Issue , 1998, Pages 216-219

  Ker, Ming Dou ^a   Chang, Hun Hsien ^a   Wang, Chen Chia ^a   Yeng, Horng Ru ^a   Tsao, Y F ^a  

^a INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

CELLULAR ARRAYS; ELECTRIC DISCHARGES; GATES (TRANSISTOR); INTEGRATED CIRCUIT LAYOUT;

CELL LIBRARY; DYNAMIC-FLOATING-GATE CIRCUIT DESIGN; ELECTROSTATIC DISCHARGES (ESD);

CMOS INTEGRATED CIRCUITS;

EID: 0031623456     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (8)