Accuracy analysis of layout parasitic extraction based on Boolean methods

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 2, Issue , 1998, Pages 394-397

  Brambilla, Angelo ^a   Mancini, Paolo ^a  

^a POLITECNICO DI MILANO   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

BOOLEAN FUNCTIONS; CAPACITANCE; ELECTRIC NETWORK ANALYSIS; ERROR ANALYSIS; SEMICONDUCTOR DEVICE STRUCTURES;

LAYOUT PARASITIC EXTRACTION (LPE) METHOD; SUBMICRON LAYOUT TECHNOLOGY;

INTEGRATED CIRCUIT LAYOUT;

EID: 0031622868     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (7)