Validation of an accurate and simple delay model and its application to voltage scaling

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 2, Issue , 1998, Pages 101-104

  Njolstad, Tormod ^a   Aas, Einar J ^a  

^a NORWEGIAN UNIVERSITY OF SCIENCE AND TECHNOLOGY   (Norway)

Author keywords

[No Author keywords available]

Indexed keywords

ADDERS; CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; DIGITAL FILTERS; ELECTRIC NETWORK ANALYSIS; ENERGY UTILIZATION; GATES (TRANSISTOR); INTEGRATED CIRCUIT TESTING; MATHEMATICAL MODELS; MICROPROCESSOR CHIPS; PARALLEL PROCESSING SYSTEMS; SENSITIVITY ANALYSIS;

DELAY CALCULATORS; DELAY ESTIMATION MODELS;

DELAY CIRCUITS;

EID: 0031622865     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (11)