Novel digit-serial systolic array implementation of Euclid's algorithm for division in GF(2m)

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 2, Issue , 1998, Pages 478-481

  Guo, Jyh Huei ^a   Wang, Chin Liang ^a  

^a NATIONAL TSING HUA UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTATIONAL METHODS; COMPUTER ARCHITECTURE; DATA FLOW ANALYSIS; DIVIDING CIRCUITS (ARITHMETIC); FAULT TOLERANT COMPUTER SYSTEMS; VLSI CIRCUITS;

DIGITAL-SERIAL SYSTOLIC ARRAYS; EUCLID'S ALGORITHM;

SYSTOLIC ARRAYS;

EID: 0031622755     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (17)