Flexible MPEG audio decoder layer III chip architecture

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 4, Issue , 1998, Pages 37-40

  Singh, P ^a   Moreno, W ^a   Ranganathan, N ^a   Neinhaus, H ^a  

^a UNIVERSITY OF SOUTH FLORIDA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER ARCHITECTURE; COMPUTER SIMULATION; COSINE TRANSFORMS; DATA COMPRESSION; DECODING; DIGITAL FILTERS; PIPELINE PROCESSING SYSTEMS; STANDARDS; VLSI CIRCUITS;

FAST HARTLEY TRANSFORMS (FHT); INVERSE MODIFIED DISCRETE COSINE TRANSFORMS (IMDCT); MOVING PICTURE EXPERTS GROUP (MPEG) STANDARDS;

DIGITAL SIGNAL PROCESSING;

EID: 0031622510     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (7)