Minimizing the effects of tolerance faults on hardware realizations of cellular neural networks

Proceedings of the IEEE International Workshop on Cellular Neural Networks and their Applications

Volumn , Issue , 1998, Pages 385-390

  Tetzlaff, R ^a   Kunz, R ^a   Geis, G ^a   Wolf, D ^a  

^a GOETHE UNIVERSITY   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTER SIMULATION; FAULT TOLERANT COMPUTER SYSTEMS; LINEAR INTEGRATED CIRCUITS; MICROPROCESSOR CHIPS; VLSI CIRCUITS;

TOLERANCE FAULT EFFECTS;

CELLULAR NEURAL NETWORKS;

EID: 0031621814     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (10)