Novel digit-serial systolic array for modular multiplication

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 2, Issue , 1998, Pages 177-180

  Guo, Jyh Huei ^a   Wang, Chin Liang ^a  

^a NATIONAL TSING HUA UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTER ARCHITECTURE; CRYPTOGRAPHY; INTEGRATED CIRCUIT LAYOUT; SYSTOLIC ARRAYS; VLSI CIRCUITS;

DIGIT-SERIAL SYSTOLIC MODULAR MULTIPLIERS; MONTGOMERY ALGORITHM;

MULTIPLYING CIRCUITS;

EID: 0031618671     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (13)