Open-loop full CMOS 103 MHz -61 dB THD S/H circuit

Proceedings of the Custom Integrated Circuits Conference

Volumn , Issue , 1998, Pages 381-383

  Hadidi, Khayrollah ^a   Sasaki, Masahiro ^a   Watanabe, Tadatoshi ^a   Muramatsu, Daigo ^a   Matsumoto, Takashi ^a  

^a URMIA UNIVERSITY   (Iran)

Author keywords

[No Author keywords available]

Indexed keywords

DIGITAL INTEGRATED CIRCUITS; ELECTRIC DISTORTION; INTEGRATED CIRCUIT LAYOUT;

SAMPLE-AND-HOLD CIRCUITS; TOTAL HARMONIC DISTORTION (THD);

CMOS INTEGRATED CIRCUITS;

EID: 0031617340     PISSN: 08865930     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (4)