Effects of post-oxidation annealing on 3nm-thick low-temperature-grown gate oxide

Applied Surface Science

Volumn 117-118, Issue , 1997, Pages 241-244

  Sakoda, Tomoyuki ^a   Matsumura, Mieko ^a   Nishioka, Yasushiro ^a  

^a Texas Instruments Japan Ltd   (Japan)

Author keywords

Interface trap density; Low temperature growth; Post oxidation annealing; Ultrathin gate oxides

Indexed keywords

ANNEALING; INTERFACES (MATERIALS); LEAKAGE CURRENTS; OXIDES;

INTERFACE TRAP DENSITY; POST OXIDATION ANNEALING;

GATES (TRANSISTOR);

EID: 0031548421     PISSN: 01694332     EISSN: None     Source Type: Journal    
DOI: 10.1016/S0169-4332(97)80087-6     Document Type: Article

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