Parallel BIST architecture for CAMs

Electronics Letters

Volumn 33, Issue 1, 1997, Pages 30-31

  Kang, Yong Seok ^a   Lee, Jong Cheol ^a   Kang, Sungho ^a  

^a Yonsei University   (South Korea)

Author keywords

Built in self test; Content addressable storage; Parallel algorithms

Indexed keywords

CELLULAR ARRAYS; DECODING; ERROR DETECTION; FAILURE ANALYSIS; LOGIC CIRCUITS; MASKS; PARALLEL ALGORITHMS; RANDOM ACCESS STORAGE; SEMICONDUCTOR STORAGE; SHIFT REGISTERS; TRANSISTORS;

BIT SHIFT REGISTER; BUILT IN SELF TEST; DECODER; FAULT MODELS;

ASSOCIATIVE STORAGE;

EID: 0031546305     PISSN: 00135194     EISSN: None     Source Type: Journal    
DOI: 10.1049/el:19970020     Document Type: Article

References (3)

1. GOOR, V.: 'Testing semiconductor memories; Theory and practice' (John Wiley & Sons, Singapore, 1995)
2. ELM, C., and TAVANGARIAN, D.: 'Associative search based test algorithm for test acceleration in FAST-RAMs'. IEEE Int. Workshop on Memory Testing, 1993. pp. 38-43
3. MAZUMDER, P., PATEL, J., and FUCHS, W.: 'Methodology for testing embedded content addressable memories'. IEEE Trans. CAD, 1988, pp. 11-20