-
1
-
-
0026977028
-
Automatic Gate-Level Synthesis of Speed-Independent Circuits
-
P.A. Beerel and T.H.-Y Meng, "Automatic Gate-Level Synthesis of Speed-Independent Circuits," Proc. ICCAD, pp. 581-586, 1992.
-
(1992)
Proc. ICCAD
, pp. 581-586
-
-
Beerel, P.A.1
Meng, T.H.-Y.2
-
2
-
-
0026926253
-
Semi-Modularity and Testability of Speed-Independent Circuits
-
P.A. Beerel and T.H.-Y Meng, "Semi-Modularity and Testability of Speed-Independent Circuits," Integration, the VLSI J., vol. 13, pp. 301-322, 1992.
-
(1992)
Integration, the VLSI J.
, vol.13
, pp. 301-322
-
-
Beerel, P.A.1
Meng, T.H.-Y.2
-
4
-
-
25644443013
-
Automatic Synthesis and Verification of Hazard-Free Control Circuits from Asynchronous Finite State Machine Specifications
-
T.A. Chu, "Automatic Synthesis and Verification of Hazard-Free Control Circuits from Asynchronous Finite State Machine Specifications," Proc. ICCD, pp. 407-413, 1992.
-
(1992)
Proc. ICCD
, pp. 407-413
-
-
Chu, T.A.1
-
7
-
-
0026175766
-
Algorithms for Synthesis of Hazard-Free Asynchronous Circuits
-
L. Lavagno, K. Keutzer, and A. Sangiovanni Vincentelli, "Algorithms for Synthesis of Hazard-Free Asynchronous Circuits," Proc. 28th Design Automation Conf., pp. 302-308, 1991.
-
(1991)
Proc. 28th Design Automation Conf.
, pp. 302-308
-
-
Lavagno, L.1
Keutzer, K.2
Sangiovanni Vincentelli, A.3
-
8
-
-
0026997840
-
Solving the State Assignment Problem for STG
-
L. Lavagno, C.W. Moon, R.K. Brayton, and A. Sangiovanni Vincentelli, "Solving the State Assignment Problem for STG," Proc. 29th Design Automation Conf., pp. 568-572, 1992.
-
(1992)
Proc. 29th Design Automation Conf.
, pp. 568-572
-
-
Lavagno, L.1
Moon, C.W.2
Brayton, R.K.3
Sangiovanni Vincentelli, A.4
-
9
-
-
0028018595
-
Direct Synthesis of Asynchronous Hazard-Free Circuits Based on Lock Relation and MG-Decomposition from STGs
-
K.J. Lin, J.W. Kuo, and C.S. Lin, "Direct Synthesis of Asynchronous Hazard-Free Circuits Based on Lock Relation and MG-Decomposition from STGs," Proc. European Conf. Design Automation, pp. 178-183, 1994.
-
(1994)
Proc. European Conf. Design Automation
, pp. 178-183
-
-
Lin, K.J.1
Kuo, J.W.2
Lin, C.S.3
-
10
-
-
0028369535
-
Specification and Analysis of Self-Timed Circuits
-
M.A. Kishinevsky, A.Y. Kondratyev, and A.R. Taubin, "Specification and Analysis of Self-Timed Circuits," J VLSI Signal Processing, vol. 7, pp. 117-135, 1994.
-
(1994)
J VLSI Signal Processing
, vol.7
, pp. 117-135
-
-
Kishinevsky, M.A.1
Kondratyev, A.Y.2
Taubin, A.R.3
-
11
-
-
0028590415
-
Basic Gate Implementation of Speed-Independent Circuits
-
A. Kondratyev, M. Kishinevsky, B. Lin, P. Vanbekbergen, and A. Yakovlev. "Basic Gate Implementation of Speed-Independent Circuits," Proc. 31th Design Automation Conf., pp. 56-62, 1994.
-
(1994)
Proc. 31th Design Automation Conf.
, pp. 56-62
-
-
Kondratyev, A.1
Kishinevsky, M.2
Lin, B.3
Vanbekbergen, P.4
Yakovlev, A.5
-
12
-
-
0022879965
-
Compiling Communication Process into DelayInsensitive VLSI Circuits
-
A.J. Martin, "Compiling Communication Process into DelayInsensitive VLSI Circuits," J Distributed Computing, vol. 1, pp. 226-234, 1986.
-
(1986)
J Distributed Computing
, vol.1
, pp. 226-234
-
-
Martin, A.J.1
-
15
-
-
0022219486
-
Synthesis of Delay-Insensitive Modules
-
C.E. Molnar, T.P. Fang, and F.U. Rosenberger, "Synthesis of Delay-Insensitive Modules," Proc. Chape Hill Conf. VLSI, pp. 67-86, 1985.
-
(1985)
Proc. Chape Hill Conf. VLSI
, pp. 67-86
-
-
Molnar, C.E.1
Fang, T.P.2
Rosenberger, F.U.3
-
16
-
-
0027101103
-
Synthesis of Hazard-Free Asynchronous Circuits from Graphical Specifications
-
C.W. Moon, P.R. Stephan, and R.K. Brayton, "Synthesis of Hazard-Free Asynchronous Circuits from Graphical Specifications," Proc. Int'l Conf. Computer Aided Design, pp. 322-325, 1991.
-
(1991)
Proc. Int'l Conf. Computer Aided Design
, pp. 322-325
-
-
Moon, C.W.1
Stephan, P.R.2
Brayton, R.K.3
-
17
-
-
0024645936
-
Petri Nets: Properties, Analysis and Applications
-
T. Murata, "Petri Nets: Properties, Analysis and Applications," Proc. IEEE, vol. 77, no. 4, pp. 541-580, 1989.
-
(1989)
Proc. IEEE
, vol.77
, Issue.4
, pp. 541-580
-
-
Murata, T.1
-
18
-
-
0027831840
-
Polynomial Algorithm for the Synthesis of Hazard-Free Circuits from STGs
-
E. Paster and J. Cortadella, "Polynomial Algorithm for the Synthesis of Hazard-Free Circuits from STGs," Proc. Int'l Coonf. Computer Aided Design, pp. 250-254, 1993.
-
(1993)
Proc. Int'l Coonf. Computer Aided Design
, pp. 250-254
-
-
Paster, E.1
Cortadella, J.2
-
19
-
-
0024683698
-
Micropipelines
-
I.E. Sutherland, "Micropipelines," Comm. ACM, vol. 32, no. 6, pp. 720-738, 1989.
-
(1989)
Comm. ACM
, vol.32
, Issue.6
, pp. 720-738
-
-
Sutherland, I.E.1
-
21
-
-
0025560646
-
Optimized Synthesis of Asynchronous Control Circuits from Graph-theoretic Specifications
-
P. Vanbekbergen, F. Catthoor, J.V. Meerbergen, and H.D. Man, "Optimized Synthesis of Asynchronous Control Circuits from Graph-theoretic Specifications," Proc. Int'l Conf. Computer Aided Design, pp. 184-187, 1990.
-
(1990)
Proc. Int'l Conf. Computer Aided Design
, pp. 184-187
-
-
Vanbekbergen, P.1
Catthoor, F.2
Meerbergen, J.V.3
Man, H.D.4
-
23
-
-
0026882866
-
Beware the Isochronic Fork
-
K. Van Berkel, "Beware the Isochronic Fork," Integration VLSI J, vol. 13, no. 2, pp. 103-128, 1992.
-
(1992)
Integration VLSI J
, vol.13
, Issue.2
, pp. 103-128
-
-
Van Berkel, K.1
-
25
-
-
0026259615
-
A Zero-Overhead Self-Timed 160ns 54b CMOS Divider
-
Nov.
-
T.E. Williams, and M.A. Horowitz, "A Zero-Overhead Self-Timed 160ns 54b CMOS Divider," IEEE J. Solid-State Circuits, pp. 1,651-1,661, Nov. 1991.
-
(1991)
IEEE J. Solid-State Circuits
, pp. 1651-1661
-
-
Williams, T.E.1
Horowitz, M.A.2
-
27
-
-
33747106874
-
Synthesis and Optimization of Asynchronous Controllers Based on Extended Lock Graph Theory
-
C. Ykman-Couvreur, B. Lin, G. Goossens, and H.D. Man, "Synthesis and Optimization of Asynchronous Controllers Based on Extended Lock Graph Theory," Proc. European Conf. Design Automation, pp. 512-517, 1993.
-
(1993)
Proc. European Conf. Design Automation
, pp. 512-517
-
-
Ykman-Couvreur, C.1
Lin, B.2
Goossens, G.3
Man, H.D.4
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