2.4-Gb/s CMOS clock recovering 1:8 demultiplexer

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue , 1997, Pages 69-70

  Soda, M ^a   Tezuka, H ^a   Shioiri, S ^a   Tanabe, A ^a   Furukawa, A ^a   Togo, M ^a   Tamura, T ^a   Yoshida, K ^a  

^a NEC CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; GATES (TRANSISTOR); INTEGRATED CIRCUIT LAYOUT; PHASE COMPARATORS; PHASE LOCKED LOOPS; SYNCHRONIZATION; TIMING CIRCUITS; VARIABLE FREQUENCY OSCILLATORS;

DEMULTIPLEXERS;

MULTIPLEXING EQUIPMENT;

EID: 0031384336     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (3)