High performance dual-gate FD-SOI CMOS process with an ultra thin TiSi2

IEEE International SOI Conference

Volumn , Issue , 1997, Pages 24-25

  Nakamura, H ^a   Imai, K ^a   Onishi, H ^a   Kumagai, K ^a   Yamada, T ^a   Iwaki, K ^a   Matsubara, Y ^a   Ishigami, T ^a   Kurosawa, S ^a   Horiuchi, T ^a  

^a NEC CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; ELECTRIC RESISTANCE; INTEGRATED CIRCUIT MANUFACTURE; MOSFET DEVICES; RANDOM ACCESS STORAGE; SEMICONDUCTOR DEVICE STRUCTURES; TITANIUM COMPOUNDS; ULTRATHIN FILMS;

SHEET RESISTANCE;

SILICON ON INSULATOR TECHNOLOGY;

EID: 0031383713     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (3)