Improving the accuracy of on-chip parasitic extraction

IEEE Topical Meeting on Electrical Performance of Electronic Packaging

Volumn , Issue , 1997, Pages 42-45

  Huang, Ching Chao ^a   Oh, Kyung Suk ^a   Wang, Shun Lien ^a   Panchapakesan, Sridhar ^a  

^a Technology Modeling Associates Inc   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE; COMPUTER SIMULATION; MONTE CARLO METHODS; REGRESSION ANALYSIS; SEMICONDUCTOR DEVICE MODELS;

LAYOUT PARAMETER EXTRACTION (LPE);

INTEGRATED CIRCUIT LAYOUT;

EID: 0031382580     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (8)