3D Global Interconnect Parameter Extractor for full-chip global critical path analysis

IEEE Topical Meeting on Electrical Performance of Electronic Packaging

Volumn , Issue , 1997, Pages 46-49

  Oh, S Y ^a   Okasaki, K ^a   Moll, J ^a   Nakagawa, O S ^a   Chang, N ^a  

^a HEWLETT PACKARD LABORATORIES   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; COMPUTER WORKSTATIONS; CRITICAL PATH ANALYSIS; INTERCONNECTION NETWORKS;

GLOBAL INTERCONNECT PARAMETER EXTRACTOR (GIPER);

ELECTRIC NETWORK PARAMETERS;

EID: 0031378661     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (3)