Efficient multiplierless FIR filter chip with variable-length taps

IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation

Volumn , Issue , 1997, Pages 412-420

  Yoon, SungHyun ^a   Sunwoo, Myung H ^a  

^a Ajou University   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTER AIDED LOGIC DESIGN; INTEGRATED CIRCUIT LAYOUT; LOGIC GATES; MATHEMATICAL MODELS; MICROPROCESSOR CHIPS; MULTIPLEXING EQUIPMENT; VLSI CIRCUITS;

DATA REUSE STRUCTURE; RECURRENT COEFFICIENT SCHEME;

DIGITAL FILTERS;

EID: 0031376069     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (12)