Bias optimization for switched capacitor amplifiers

IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing

Volumn 44, Issue 12, 1997, Pages 985-989

  Opris, Ion E ^b   Lewicki, Laurence D ^a,b  

^a IEEE

^b NATIONAL SEMICONDUCTOR CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BANDWIDTH; CAPACITORS; COMPUTER SIMULATION; ELECTRIC NETWORK ANALYSIS; OPTIMIZATION; SWITCHING CIRCUITS;

SWITCHED CAPACITOR CIRCUITS;

OPERATIONAL AMPLIFIERS;

EID: 0031375697     PISSN: 10577130     EISSN: None     Source Type: Journal    
DOI: 10.1109/82.644533     Document Type: Article

References (5)

1. B. Y. Kamath, R. G. Meyer, and P. R. Gray,"Relationship between frequency response and settling time of operational amplifiers," IEEE J. Solid-State Circuits, vol. SC-9, pp. 347-352, Dec. 1974.
2. S. M. Sze, Physics of Semiconductor Devices, 2nd ed. New York: Wiley, p. 28, 1981.
3. D. M. Monticelli,"A quad CMOS single-supply op amp with rail-to-rail output swing," IEEE J. Solid-State Circuits, vol. SC-21, pp. 1026-1034, Dec. 1986.
4. W. B. Jett Jr.,"CMOS op amp bias circuit," U.S. Patent 4489282, Dec. 18, 1984.
5. K. S. Kundrt, The Designer's Guide to Spice& Spectre. Boston, MA: Kluwer Academic, 1995.