Pixel-parallel image processor using logic pitch-matched to dynamic memory

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue , 1997, Pages 57-58

  Gealow, Jeffrey C ^a   Sodini, Charles G ^a  

^a MASSACHUSETTS INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; EDGE DETECTION; FLIP FLOP CIRCUITS; GATES (TRANSISTOR); IMAGE PROCESSING; INTEGRATED CIRCUIT MANUFACTURE; LOGIC GATES; RANDOM ACCESS STORAGE; TIMING CIRCUITS;

LOGIC PITCH; PIXEL PARALLEL IMAGE PROCESSORS;

MICROPROCESSOR CHIPS;

EID: 0031374802     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (3)