Low-cost massively-parallel interconnect test method for MCM substrates

IEEE International Test Conference (TC)

Volumn , Issue , 1997, Pages 370-378

  Newman, K E ^a   Keezer, D C ^a  

^a GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE MEASUREMENT; COST EFFECTIVENESS; ELECTRIC CONDUCTIVITY MEASUREMENT; MULTICHIP MODULES; SUBSTRATES;

BOUNDARY SCAN REGISTERS; MASSIVELY INTERCONNECT TEST METHOD;

INTEGRATED CIRCUIT TESTING;

EID: 0031367610     PISSN: 10893539     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (9)