Block processing unit in a single-chip MPEG-2 video encoder LSI

IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation

Volumn , Issue , 1997, Pages 459-468

  Katayama, Yoichi ^a   Kitsuki, Toshiaki ^a   Ooi, Yasushi ^a  

^a NEC CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; CMOS INTEGRATED CIRCUITS; ELECTRIC LOSSES; IMAGE CODING; INTEGRATED CIRCUIT LAYOUT; MATHEMATICAL TRANSFORMATIONS; MICROPROCESSOR CHIPS; PIPELINE PROCESSING SYSTEMS; STANDARDS; TIMING CIRCUITS; TRANSISTORS; VIDEO SIGNAL PROCESSING;

BLOCK PROCESSING UNIT; DISCRETE COSINE TRANSFORM (DCT); INVERSE DISCRETE COSINE TRANSFORM (IDCT); MOTION PICTURE EXPERTS GROUP (MPEG);

LSI CIRCUITS;

EID: 0031359471     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (11)