Conductance DLTS analysis of the correlation between power slump and gate lag

Technical Digest - GaAs IC Symposium (Gallium Arsenide Integrated Circuit)

Volumn , Issue , 1997, Pages

  Leoni, R E ^a   Bao, J W ^a   Du, X ^a   Shirokov, M ^a   Hwang, J C M ^a  

^a LEHIGH UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CORRELATION METHODS; DEEP LEVEL TRANSIENT SPECTROSCOPY; GATES (TRANSISTOR); IONIZATION; PRESSURE EFFECTS; SEMICONDUCTING GALLIUM ARSENIDE;

GATE LAG;

MESFET DEVICES;

EID: 0031356994     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)