An area-efficient pipelined VLSI architecture for decoding of Reed-Solomon codes based on a time-domain algorithm

IEEE Transactions on Circuits and Systems for Video Technology

Volumn 7, Issue 6, 1997, Pages 864-871

  Hsu, Jah Ming ^b   Wang, Chin Liang ^a,b  

^a IEEE

^b NATIONAL TSING HUA UNIVERSITY   (Taiwan)

Author keywords

Error correcting code; Pipelined architecture; Reed Solomon code; Reed Solomon decoder; Time domain Berlekamp Massey algorithm; VLSI

Indexed keywords

ALGORITHMS; CODES (SYMBOLS); DECODING; ERROR CORRECTION; IMAGE CODING; TIME DOMAIN ANALYSIS;

DECODERS;

VLSI CIRCUITS;

EID: 0031356732     PISSN: 10518215     EISSN: None     Source Type: Journal    
DOI: 10.1109/76.644066     Document Type: Article

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