Fault model extension for diagnosing custom cell fails

IEEE International Test Conference (TC)

Volumn , Issue , 1997, Pages 617-624

  Bartenstein, Thomas ^a   Vandling, Gilbert ^a  

^a IBM   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ERROR ANALYSIS; INTEGRATED CIRCUIT LAYOUT; SEMICONDUCTOR DEVICE MODELS;

STUCK AT FAULT MODELS;

INTEGRATED CIRCUIT TESTING;

EID: 0031354476     PISSN: 10893539     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)