Compilers for instruction-level parallelism

Computer

Volumn 30, Issue 12, 1997, Pages 63-69

  Schlansker, Michael ^a,f,g   Conte, Thomas M ^b   Dehnert, James ^c,h   Ebcioglu, Kemal ^d,i   Fang, Jesse Z ^e   Thompson, Carol L ^a,h,j  

^a HEWLETT PACKARD LABORATORIES   (United States)

^b NORTH CAROLINA STATE UNIVERSITY   (United States)

^c HEWLETT PACKARD ENTERPRISE   (United States)

^d IBM T J WATSON RESEARCH CENTER   (United States)

^e INTEL CORPORATION   (United States)

^f UNIVERSITY OF MICHIGAN   (United States)

^g IEEE   (United States)

^h UNIVERSITY OF CALIFORNIA   (United States)

ⁱ UNIVERSITY AT BUFFALO   (United States)

^j IBM TJ Watson Research Center ^*  (United States)

more..

Author keywords

[No Author keywords available]

Indexed keywords

C (PROGRAMMING LANGUAGE); COMPUTER SOFTWARE; DATA STRUCTURES; MICROPROCESSOR CHIPS; PARALLEL PROCESSING SYSTEMS; PIPELINE PROCESSING SYSTEMS; REDUCED INSTRUCTION SET COMPUTING; RESPONSE TIME (COMPUTER SYSTEMS); SYNCHRONIZATION;

ADVANCED MEMORY ARCHITECTURES; INSTRUCTION LEVEL PARALLELISM (ILP); VERY LONG INSTRUCTION WORD (VLIW) PROCESSOR;

PROGRAM COMPILERS;

EID: 0031354358     PISSN: 00189162     EISSN: None     Source Type: Trade Journal    
DOI: 10.1109/2.642817     Document Type: Review

References (13)

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2. J. Ruttenberg et al., "Software Pipelining Showdown: Optimal vs. Heuristic Methods in a Production Compiler," Proc. Programming Language Design and Implementation, ACM Press, New York, 1996, pp. 1-11.
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8. S.-M. Moon and K. Ebcioglu, "An Efficient Resource-Constrained Global Scheduling Technique for Superscalar and VLIW Processors," Proc. 25th Int'l Symp. Microarchitecture, IEEE CS Press, Los Alamitos, Calif., 1992, pp. 55-71.
9. V. Kathail, M.S. Schlansker, and B.R. Rau, HPL Play-Doh Architecture Specification: Version 1.0, Tech. Report HPL-93-80, Hewlett-Packard Laboratories, Palo Alto, Calif., 1993.
10. G.M. Silberman and K. Ebcioglu, "An Architectural Framework for Supporting Heterogeneous Instruction-Set Architectures," Computer, June 1993, pp. 39-56.
11. S.A. Mahlke et al., "Effective Compiler Support for Predicated Execution Using the Hyperblock," Proc. 25th Ann. Int'l Symp. Microarchitecture, IEEE CS Press, Los Alamitos, Calif., 1992, pp. 45-54.
12. D.M. Gallagher et al., "Dynamic Memory Disambiguation Using the Memory Conflict Buffer," Proc. Architectural Support for Programming Languages and Operating Systems, ACM Press, New York, 1994, pp. 183-193.
13. R.E. Hank, W.W. Hwu, and B.R. Rau, "Region-Based Compilation: Introduction, Motivation, and Initial Experience," Int'l J. Parallel Programming, Vol. 25, No. 2, 1997, pp. 113-146.