Effect of express lots on production dispatching rule scheduling and cost in final test process of LSI manufacturing system

IEEE International Symposium on Semiconductor Manufacturing Conference, Proceedings

Volumn , Issue , 1997, Pages

  Chikamura, Akihisa ^a   Nakamae, Koji ^a   Fujioka, Hiromu ^a  

^a OSAKA UNIVERSITY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; COST EFFECTIVENESS; INTEGRATED CIRCUIT TESTING; LSI CIRCUITS; MICROPROCESSOR CHIPS;

DISPATCHING RULE SCHEDULING; FIRST IN FIRST OUT (FIFO) RULE;

INTEGRATED CIRCUIT MANUFACTURE;

EID: 0031348038     PISSN: 10788743     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (3)