Design and realization of a two input fuzzy chip running at a rate of 80 ns

Annual Conference of the North American Fuzzy Information Processing Society - NAFIPS

Volumn , Issue , 1997, Pages 329-334

  Falchieri, D ^a   Gabrielli, A ^a   Gandolfi, E ^a   Masetti, M ^a  

^a UNIVERSITY OF BOLOGNA   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER HARDWARE DESCRIPTION LANGUAGES; FUZZY SETS; INTEGRATED CIRCUIT LAYOUT; PIPELINE PROCESSING SYSTEMS; VLSI CIRCUITS;

FUZZY CHIPS;

MICROPROCESSOR CHIPS;

EID: 0031344940     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (11)