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Volumn , Issue , 1997, Pages 236-237
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Mapping a real-time video algorithm to a context-switched FPGA
a
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Author keywords
[No Author keywords available]
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Indexed keywords
CONFIGURATION MEMORY PLANES;
FIELD PROGRAMMABLE GATE ARRAYS;
ROUTING;
TIME SHARE MODE;
COMPUTER HARDWARE;
LOGIC GATES;
MULTIPLEXING;
PARALLEL PROCESSING SYSTEMS;
RANDOM ACCESS STORAGE;
SWITCHING;
PARALLEL ALGORITHMS;
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EID: 0031339615
PISSN: 10823409
EISSN: None
Source Type: Conference Proceeding
DOI: 10.1109/FPGA.1998.707901 Document Type: Conference Paper |
Times cited : (2)
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References (4)
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