Properties of the input pattern fault model

Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors

Volumn , Issue , 1997, Pages 372-380

  Blanton, R D ^a   Hayes, John P ^a  

^a CARNEGIE MELLON UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ADDERS; COMPUTER SIMULATION; ELECTRIC NETWORK ANALYSIS; INTEGRATED CIRCUIT LAYOUT; MATHEMATICAL MODELS;

INPUT PATTERN (IP) FAULT MODEL; SINGLE STUCK LINE (SSL) FAULTS;

INTEGRATED CIRCUIT TESTING;

EID: 0031339329     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (21)