Implementations of on sensor image compression and comparisons between pixel and column parallel architectures

IEEE International Conference on Image Processing

Volumn 2, Issue , 1997, Pages 258-261

  Aizawa, K ^a   Hamamoto, T ^a   Ohtsuka, Y ^a   Hatori, M ^a   Abe, M ^a  

^a UNIVERSITY OF TOKYO   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTER ARCHITECTURE; IMAGE CODING; IMAGE COMPRESSION; IMAGE QUALITY; OBJECT RECOGNITION; PARALLEL PROCESSING SYSTEMS;

COLUMN PARALLEL ARCHITECTURES; PIXEL PARALLEL ARCHITECTURES;

IMAGE SENSORS;

EID: 0031339197     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (2)