A novel planarization technique for a high-Tc multilevel IC process

IEEE Transactions on Applied Superconductivity

Volumn 7, Issue 4, 1997, Pages 3834-3839

  Marathe, Amit P ^b   Van Duzer, Theodore ^a,c   Lee, Luke P ^d  

^a IEEE

^b ADVANCED MICRO DEVICES   (United States)

^c UNIVERSITY OF CALIFORNIA   (United States)

^d University of California   (United States)

Author keywords

High temperature superconductors; Integrated circuit fabrication; Planarization; Superconducting circuits

Indexed keywords

ATOMIC FORCE MICROSCOPY; CRITICAL CURRENT DENSITY (SUPERCONDUCTIVITY); CURRENT VOLTAGE CHARACTERISTICS; DIGITAL INTEGRATED CIRCUITS; HIGH TEMPERATURE SUPERCONDUCTORS; INTEGRATED CIRCUIT MANUFACTURE; OXIDE SUPERCONDUCTORS; STRONTIUM COMPOUNDS; SUPERCONDUCTING FILMS; SURFACE ROUGHNESS; YTTRIUM COMPOUNDS;

COMPLEMENTARY MASK PLANARIZATION (COMP); INTEGRATED CIRCUIT FABRICATION; SUPERCONDUCTING CIRCUITS;

SUPERCONDUCTING DEVICES;

EID: 0031337747     PISSN: 10518223     EISSN: None     Source Type: Journal    
DOI: 10.1109/77.659435     Document Type: Article

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