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Volumn 44, Issue 11, 1997, Pages 1888-1895

A standby current limited performance figure of merit for deep sub-micron CMOS

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE; ELECTRIC CURRENTS; ELECTRIC INVERTERS; GATES (TRANSISTOR); NAND CIRCUITS;

EID: 0031277334     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/16.641357     Document Type: Article
Times cited : (7)

References (10)
  • 4
    • 34648828535 scopus 로고    scopus 로고
    • "Scaling high performance CMOS into the 21st century," in 4th Int. Conf. VLSI and CAD, Seoul, Korea, 1995, pp. 5-12.
    • R. A. Chapman, "Scaling high performance CMOS into the 21st century," in Proc. 4th Int. Conf. VLSI and CAD, Seoul, Korea, 1995, pp. 5-12.
    • Proc.
    • Chapman, R.A.1
  • 6
    • 0027969375 scopus 로고    scopus 로고
    • "Low-voltage CMOS device scaling," in 1994ISSCC, 1994, pp. 86-87.
    • C. Hu, "Low-voltage CMOS device scaling," in Proc. Dig. 1994ISSCC, 1994, pp. 86-87.
    • Proc. Dig.
    • Hu, C.1
  • 8
    • 0029292398 scopus 로고    scopus 로고
    • "Low power microelectronics: Retrospect and prospect," vol. 83, pp. 42-58, 1995.
    • J. D. Meindl, "Low power microelectronics: Retrospect and prospect," Proc. IEEE, vol. 83, pp. 42-58, 1995.
    • Proc. IEEE
    • Meindl, J.D.1
  • 9
    • 0029702282 scopus 로고    scopus 로고
    • "An investigation of the impact of technology scaling on power wasted as short-circuit current in low voltage static CMOS circuits," in 1996 Int. Symp. Low Power Electron. Design, Monterey, CA, 1996, pp. 145-150.
    • A. Chatterjee, M. Nandakumar, and I.-C. Chen, "An investigation of the impact of technology scaling on power wasted as short-circuit current in low voltage static CMOS circuits," in Proc. Dig. 1996 Int. Symp. Low Power Electron. Design, Monterey, CA, 1996, pp. 145-150.
    • Proc. Dig.
    • Chatterjee, A.1    Nandakumar, M.2    Chen, I.-C.3
  • 10


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.