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Volumn 15, Issue 11, 1997, Pages 1997-2004

Learning method for neural networks using weight perturbation of orthogonal bit sequence and its application to adaptive WDM demultiplexer

Author keywords

Learning; Neural networks; Optical demultiplexer; Perturbation; Wavelength division multiplexing (WDM)

Indexed keywords

COMMUNICATION CHANNELS (INFORMATION THEORY); CORRELATION DETECTORS; ELECTRIC NETWORK PARAMETERS; ERROR CORRECTION; FREQUENCY DIVISION MULTIPLEXING; LEARNING SYSTEMS; OPTICAL COMMUNICATION; OPTICAL CORRELATION; OPTICAL FIBERS; PERTURBATION TECHNIQUES; SIGNAL DETECTION; TRANSMITTERS;

EID: 0031274925     PISSN: 07338724     EISSN: None     Source Type: Journal    
DOI: 10.1109/50.641517     Document Type: Article
Times cited : (2)

References (15)
  • 1
    • 0024874120 scopus 로고
    • Handwritten neural recognition by multi-layered neural network with improved learning algorithm
    • K. Yamada, H. Kami, J. Tsukumo, and T. Temma, "Handwritten neural recognition by multi-layered neural network with improved learning algorithm," in Proc. IJCNN'89, 1989, vol. II, pp. 259-266.
    • (1989) Proc. IJCNN'89 , vol.2 , pp. 259-266
    • Yamada, K.1    Kami, H.2    Tsukumo, J.3    Temma, T.4
  • 2
    • 0023594761 scopus 로고
    • A hierarchical model for voluntary movement and its application to robotics
    • M. Kawato, Y. Uno, M. Isobe, and R. Suzuki, "A hierarchical model for voluntary movement and its application to robotics," in Proc. ICNN'87, 1987, vol. 4, pp. 573-582.
    • (1987) Proc. ICNN'87 , vol.4 , pp. 573-582
    • Kawato, M.1    Uno, Y.2    Isobe, M.3    Suzuki, R.4
  • 4
    • 3843121892 scopus 로고
    • Neural processing type optical WDM demultiplexer using a grating
    • Aug.
    • S. Aisawa, K. Noguchi, T. Matsumoto, H. Tsunetsugu, and M. Yuda, "Neural processing type optical WDM demultiplexer using a grating," Trans. IEICE, vol. J78-B-I, no. 8, pp. 343-355, Aug. 1995.
    • (1995) Trans. IEICE , vol.J78-B-I , Issue.8 , pp. 343-355
    • Aisawa, S.1    Noguchi, K.2    Matsumoto, T.3    Tsunetsugu, H.4    Yuda, M.5
  • 5
    • 0027809760 scopus 로고
    • Very-high-speed analog neural network LSI implementation using super self-aligned Si bipolar process technology
    • Oct.
    • S. Aisawa, K. Noguchi, M. Koga, T. Matsumoto, and Y. Amemiya, "Very-high-speed analog neural network LSI implementation using super self-aligned Si bipolar process technology," in Proc. IJCNN'93, Oct. 1993, vol. 1, pp. 895-898.
    • (1993) Proc. IJCNN'93 , vol.1 , pp. 895-898
    • Aisawa, S.1    Noguchi, K.2    Koga, M.3    Matsumoto, T.4    Amemiya, Y.5
  • 6
    • 0028446452 scopus 로고
    • Very-high-speed analog neural network LSI using super self-aligned Si bipolar process technology
    • June
    • S. Aisawa, K. Noguchi, M. Koga, T. Matsumoto, and Y. Amemiya, "Very-high-speed analog neural network LSI using super self-aligned Si bipolar process technology," IEICE Trans. Electron., vol. E-77C, no. 6, pp. 1005-1008, June 1994.
    • (1994) IEICE Trans. Electron. , vol.E-77C , Issue.6 , pp. 1005-1008
    • Aisawa, S.1    Noguchi, K.2    Koga, M.3    Matsumoto, T.4    Amemiya, Y.5
  • 7
    • 0029487528 scopus 로고
    • Implementation of simplified multilayer neural networks with on-chip learning
    • H. Hikawa, "Implementation of simplified multilayer neural networks with on-chip learning," in Proc. ICNN'95, 1995, pp. 1633-1637.
    • (1995) Proc. ICNN'95 , pp. 1633-1637
    • Hikawa, H.1
  • 8
    • 0028495068 scopus 로고
    • An all-analog expandable neural network LSI with on-chip back-propagation learning
    • Sept.
    • T. Morie and Y. Amemiya, "An all-analog expandable neural network LSI with on-chip back-propagation learning," IEEE J. Solid-State Circuits, vol. 29, pp. 1086-1093, Sept. 1994.
    • (1994) IEEE J. Solid-State Circuits , vol.29 , pp. 1086-1093
    • Morie, T.1    Amemiya, Y.2
  • 9
    • 0025465244 scopus 로고
    • Novel learning method for analog neural networks
    • July
    • T. Matsumoto and M. Koga, "Novel learning method for analog neural networks," Electron. Lett., vol. 26, no. 15, pp. 1136-1137, July 1990.
    • (1990) Electron. Lett. , vol.26 , Issue.15 , pp. 1136-1137
    • Matsumoto, T.1    Koga, M.2
  • 10
    • 0027617758 scopus 로고
    • Hardware implementation of the multi-frequency learning method for analog neural networks
    • June
    • H. Miyao, M. Koga, and T. Matsumoto, "Hardware implementation of the multi-frequency learning method for analog neural networks," IEICE Trans. Inform. Syst., vol. E76-D, no. 6, pp. 717-719, June 1993.
    • (1993) IEICE Trans. Inform. Syst. , vol.E76-D , Issue.6 , pp. 717-719
    • Miyao, H.1    Koga, M.2    Matsumoto, T.3
  • 11
    • 0011468576 scopus 로고
    • Analog VLSI implementation of adaptive algorithms by an extended Hebbian learning
    • Mar.
    • T. Morie, O. Fujita, and Y. Amemiya, "Analog VLSI implementation of adaptive algorithms by an extended Hebbian learning," IEICE Trans. Electron., vol. E-75C, no. 3, pp. 303-311, Mar. 1992.
    • (1992) IEICE Trans. Electron. , vol.E-75C , Issue.3 , pp. 303-311
    • Morie, T.1    Fujita, O.2    Amemiya, Y.3
  • 14
    • 3843087167 scopus 로고
    • Hadamard matrix and its applications
    • Chap. 16, in Japanese
    • Z. Kiyasu, "Hadamard matrix and its applications," IEICE, 1980, Chap. 16, pp. 449-472 (in Japanese).
    • (1980) IEICE , pp. 449-472
    • Kiyasu, Z.1
  • 15
    • 0027694680 scopus 로고
    • A floating gate analog memory device for neural networks
    • Nov.
    • O. Fujita and Y. Amemiya, "A floating gate analog memory device for neural networks," IEEE Trans. Electron. Devices, vol. 40, pp. 2029-2035, Nov. 1993.
    • (1993) IEEE Trans. Electron. Devices , vol.40 , pp. 2029-2035
    • Fujita, O.1    Amemiya, Y.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.